Standard prior art complementary and differential driver designs have a single data input and use an inverter to provide the complementary phase input signal. This extra inversion between the true and complement delay paths introduces a delay difference that distorts the output signal cross-point, increases duty cycle distortion, and increases deterministic jitter. As transmission speeds increase and timing budgets shrink, these errors become a problem for high performance designs.
A typical prior art typology for complementary drivers is shown in FIG. 1. The circuit includes drivers 20 and 22; inverters 24 and 26; input A; complementary signals AT and AZ; complementary outputs Y and YZ; and output voltage Vdiff. Inverter 26 is used to generate the phase difference of true and complement output paths Y and YZ. A plot of the resulting delay skew caused by inverter 26 is shown in FIG. 2. The usual means to mitigate the impact of the extra inversion between true and complement paths is to add extra load to slow down the delay for the path with fewer inversions. Alternatively, the inverters for the longer delay path can be increased in size to speed up that path. The delay can be balanced for a particular set of process, voltage, temperature and input slew rate. Extra buffering of the input also helps reduce edge rate dependency, but will increase the propagation delays. However, the circuit will not remain in balance for all process, temperature, voltage, and input slew rate conditions. This asymmetry in delay path is also undesirable as it relies on accurate predictability of the parasitic resistance and capacitance for a given technology node.